1. Field of the Invention
The present invention relates to a vertical type MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a method of its production, and more particularly to a vertical type MISFET and a method of its production, wherein the MISFET has a trench structure.
2. Description of the Related Art
Heretofore, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been used as a kind of power devices for handling relatively large currents and large voltages. Since the MOSFET is a voltage-controlled device, the MOSFET is advantageous in that it does not require any input current. Further, in principle, since only ones of holes and electrons in great numbers are used as carriers in the MOSFET in operation, there is no effect of carrier accumulation, so that the MOSFET is excellent in switching characteristics and in anti-punch-through characteristics. Due to these characteristics, the MOSFET has been widely applied to inductive loads such as switching regulators and the like.
As for such MOSFET, there is an initial type of lateral type MOSFET, in which an operating current (drain current) flows in a direction (or, lateral direction) parallel to a main plane of a semiconductor substrate. In contrast with this initial type, recently, the vertical type MOSFET has been widely used, in which the drain current flows in a direction (or, vertical direction) perpendicular to the main plane of the semiconductor substrate. In this vertical type MOSFET, it is possible to connect a large number of cells (i.e., unit devices) in parallel with each other so as to form a MOSFET. Consequently, such vertical type MOSFET is advantageous in that it is capable of increasing its current capacity.
Here, as the most important characteristics of conventional MOSFET including the vertical type MOSFET, there are on-resistance characteristics. Since the on-resistance characteristics largely affect a switching operation of the MOSFET, it is desirable to reduce the on resistance. Consequently, even in the vertical type MOSFET, in order to enjoy the above-mentioned advantages, it is necessary to reduce the on resistance.
As a vertical type MOSFET reducing its on resistance, Japanese Patent Laid-Open No. Sho 63-23365 discloses a MOSFET shown in FIG. 16, in which: a pair of divided n.sup.+ -type source regions 53 are formed in a surface of an n.sup.- -type epitaxial layer 52 which is formed on an n.sup.+ -type substrate 51; a gate electrode 55 is formed on a gate oxide film 54 between these source regions 53. Further, formed immediately under the n.sup.+ -type source regions 53 are a pair of p.sup.+ -type base regions 56. Of these regions 56, ones immediately under the gate oxide film 54 form inverted regions when a gate voltage is controlled. The thus inverted regions function as channel regions. Further, formed in a region immediately under the gate electrode 55 forming a part of a path for a drain current is an n.sup.+ -type region 57 which functions to reduce the on resistance of the vertical MOSFET in operation. Incidentally, as shown in FIG. 16, a drain electrode 58 is oppositely disposed from a source electrode 59 in a vertical direction.
On the other hand, in the prior art disclosed in the above Japanese Patent Laid-Open No. Sho 63-23365, though it is possible to reduce the on resistance of a vertical MOSFET, there is imitation in downsizing its cells since the channel region is formed in a horizontal direction in which the gate electrode 55 is arranged. Due to this, when a large number of cells are connected in parallel with each other in the MOSFET in order to increase its current capacity, it is inevitable that a semiconductor chip thus formed increases in size.
In this respect, Japanese Patent Laid-Open No. Hei 3-55879 discloses a MOSFET in which, as shown in FIG. 17: a channel region is vertically formed; a gate electrode 64 is formed through a gate oxide film 63 in a trench (or, groove) 62 which is formed in a p.sup.+ -type substrate 61; and, formed in the bottom of the trench 62 is an n.sup.+ -type region 65, whereby an inverted region extending in a vertical direction is formed in a region immediately under the gate oxide film 63 when a gate voltage is controlled, and the thus inverted region functions as a channel region. Incidentally, the gate electrode 64 is covered by an interlayer insulation film 66.
In such prior art disclosed in the above Japanese Patent Laid-Open No. Hei 3-55879, however, a drain current does not flow in a vertical direction through the p.sup.+ -type substrate 61. Therefore, the subject matter of this prior art is not a vertical type MOSFET. In other words, this prior art merely shows a MOSFET having a construction in which a channel region is formed in a vertical direction.
As for a vertical type MOSFET which is capable of downsizing its cells, the applicant of the subject Patent application has already disclosed such vertical type MOSFET in his previous application (i.e., Japanese Patent application No. Hei 9-254671). As shown in FIG. 18, in this vertical type MOSFET: a p-type base region 73 is formed in an n.sup.- -type epitaxial layer 72 which is formed on an n.sup.+ -type substrate 71; a trench 74 is so formed as to extend across both this n.sup.- type epitaxial layer 72 and the p-type base region 73; a gate electrode 76 is formed through a gate insulation film 75 in the trench 74; an n.sup.+ -type source region 77 is formed in the p-type base region 73 so as to surround the trench 74; the gate electrode 76 is covered with an insulation (i.e., dielectric) film 78; the n.sup.+ -type source region 77 is connected with the source electrode 79; and, the n.sup.+ -type substrate 71 is connected with a drain electrode 80, whereby the vertical type MOSFET is produced.
In the vertical type MOSFET having the above construction, it is possible to improve its on-resistance characteristics, and also possible to downsize its cells since its channel region is formed in a vertical direction along a side surface of the trench 74.
However, in the prior art disclosed in the above Japanese Patent application No. Hei 9-254671, since the base region is smaller in depth than the trench, it is difficult to improve the vertical type MOSFET in its pressure-resistance characteristics.
In other words, though the vertical type MOSFET has been widely applied to inductive loads such as switching regulators and the like, when such vertical type MOSFET is applied to the inductive loads, it is necessary to improve the MOSFET in in its pressure-resistance characteristics, which requires that the base region is larger in depth than the trench.
However, when the base region is formed so as to be merely larger in depth than the trench, an RJFET component (i.e., a resistance component of a junction field-effect transistor), which is an inevitably produced undesired resistance, disadvantageously increases. FIG. 19 is a view illustrating the above, in which more specifically: when the p-type base region 73 is formed deeply in the n.sup.- -type epitaxial layer 72 formed on the n.sup.+ -type substrate 71, the RJFET component produced in the n.sup.- -type epitaxial layer 72 increases to function to increase the on resistance of this vertical type MOSFET. Incidentally, in FIG. 19: an RSUB denotes a resistance component of the n.sup.+ -type substrate 71; an Rep denotes a resistance component of the n.sup.- type epitaxial layer 72; and, Rch denotes a resistance component of the channel region.
Here, it is possible to reduce the on resistance by varying the depth and the width of the trench. However, this not only increases the Rch but also changes in shape the interlayer insulation film being formed in the trench. Consequently, there is a fear that a short fault and like failures will occur due to variations in stress imposed on the source electrode when the wire bonding to the source electrode formed on the interlayer insulation film is conducts.